A Reconfigurable Network Architecture For Parallel Prefix Counting

We propose an efficient reconfigurable parallel prefix counting network based on the recently-proposed technique of shift switching with domino logic, where the discharging signals can propagate along the switch chain asynchronously and produce a semaphore to indicate the end of each domino process. This results in a network that is fast and highly hardwarecompact. The proposed architecture for prefix counting N-1 bits involves a total of N+ cascaded simple switches and achieves a delay of (logN)( Td + ) + Tadd where Td is the time for discharging 4 cascaded precharged pass-transistors, Tadd is a full adder delay, and < Tadd. This is significantly faster than any design known to us for N ≤2 10. Another important feature of the proposed architecture is that it requires a very simple control structure, driven solely by the semaphores. This significantly reduces the hardware complexity and fully utilizes the inherent speed of the computation. Index Terms Special purpose architectures, reconfigurable architectures, digital signal processing, VLSI design, domino logic, computer arithmetic. The work was supported, in part, by National Science Foundation under grants MIP-9630870, CCR-0073469 and ....